In semiconductor fabrication processes, the photo resolution of a photoresist pattern begins to blur at about 45 nanometer (nm) half pitch, or about 90 nm pitch. As used in this disclosure, a pitch size in a pattern that can be formed using one mask without blurring is referred to as a single-mask pitch. As feature sizes decrease to 20/22 nm and beyond, various methods are used to address the resolution issue. Particularly, double exposure techniques may be used to reduce resolution using two masks.
Double exposure involves forming patterns on a single layer of a substrate using two different masks in succession. As a result, line spacing in the combined pattern can be reduced while maintaining good resolution. In a method referred to as double dipole lithography (DDL), the patterns to be formed on the layer are decomposed and formed on a first mask having only horizontal lines, and on a second mask having only vertical lines. The first and second masks are said to have 1-dimensional (1-D) patterns, which can be printed with existing lithographic tools.
Another form of double exposure is referred to as double patterning technology (DPT). Generally, a first pattern having a single mask pitch or greater is exposed, developed, and etched into the underlying dielectric layer before a second pattern that is different from the first pattern is exposed, developed, and etched into the underlying dielectric layer. The first and second patterns form an interlaced pattern in the underlying dielectric layer having features with pitch sizes as small as half of the single mask pitch. Thus, DPT generally allows for greater reduction in overall IC layout. However, DPT adds to manufacturing cost by using two layers of photoresist and doubling the number of operations to form the smaller pitch features.
While DPT methods can form features having small pitch size, they have not been entirely satisfactory in every aspect. More cost efficient methods continue to be sought.